1. Field of the Invention
The present invention relates to a sequence controller capable of programmable sequence control operations.
2. Description of the Prior Art
FIGS. 1 through 4 show a typical sequence table and a representative sequence control method utilized by prior art sequence controllers of this kind. FIGS. 5 through 8 are views illustrating how a conventional sequence controller operates. FIG. 5 shows a system block diagram of the sequence controller that controls a two-liquid mixer. In this figure, numeral 1 designates a sequence controller, 2 a tank in which to mix liquids A and B, 3 a mixer that mixes the two liquids, 4 a valve for the liquid A, 5 a valve for the liquid B, 6 a valve for discharging the liquid mixture, 7 a motor that turns the mixer 3, 8 a start push-button switch, 9 a push-button switch for resetting an emergency stop, and 10, 20 and 30 level switches for detecting the liquid level in the tank 2. The valve 4 is opened at a logical "1" and closed at "0" under control of an output 04 of the sequence controller 1. The valves 5 and 6 are operated likewise as described above under control of outputs 05 and 06, respectively. The motor 7, under control of an output 07, is started at a logical "1" and stopped at "0". The start push-button switch 8 and the emergency stop reset push-button switch 9 are connected to I8 and I9, respectively, both being inputs of the sequence controller 1. These switches are each turned on at a logical "1" and off at "0". The level switches 10, 20 and 30 are connected to inputs I10, I20 and I30, respectively. A liquid level exceeding any of these three switches causes a logical "1" to be set; when the switches remain above the level, a logical "0" is maintained. In FIG. 5, numeral 15 designates a warning lamp. Connected to an output 015, the lamp 15 is turned on at a logical "1" and off at "0".
FIG. 1 shows a sequence table describing the operating procedure for controlling the system shown in FIG. 5. More specifically, the sequence table of FIG. 1 is made up of three tables: a variable data table of FIG. 7, a detailed data table of FIG. 6, and a fixed data table of FIG. 3. The sequence is effected in accordance with a flowchart of FIG. 4 by periodically executing a table execution instruction "EXE-TBL-1" of FIG. 2. The sequence controller 1 is capable of executing such multiple tables in a row. Here, the description will be limited to the table 1 to avoid explanatory duplication.
FIG. 4 shows a flowchart outlining what the table execution instruction does.
There will now be described how the sequence controller shown in FIG. 5 works by referring to the sequence table of FIG. 1. In step ST1 of the sequence table, activation of the start push-button switch (i.e., input I8 going "1") is awaited. When the switch 8 is turned on, M11 (normal) is set to a logical "1" and step ST2 is reached. In step ST2, the output 04 is effected (i.e., only the valve 4 for liquid A is at a logical "1"; all other outputs are at a logical "0" each). The liquid A is injected into the tank 2. When the liquid level goes up to about the middle mark through liquid injection (i.e., when inputs I20 and I30 are at a logical "1" each), M11 (normal) is set to a logical "1" and step ST4 is reached. (Steps ST3, ST5 and ST8 are for error processing each.) In step ST4, the output 05 is effected (i.e., only the valve 5 for liquid B is opened at a logical " 1"; all other outputs are at a logical "0" each). The liquid B is injected into the tank 2. When the liquid level goes up to the high mark (i.e., when the .inputs I10, I20 and I30 are at a logical "1" each), M11 (normal) is set to a logical "1" and step ST6 is reached. In step ST6, the output 07 of the motor 7 is turned on to mix the liquids. In step ST7, the output 06 of the mixture discharging valve 6 is opened to have the tank 2 empty its contents. In step ST9, every output is set to a logical "0" and then step ST1 is reached again. This is how the normal sequence takes place.
The sequence table is also operated by periodically executing the table execution instruction "EXE-TBL-1" of FIG. 2. The flowchart applicable to that kind of execution is shown in FIG. 4. (The operations in FIG. 4 will be described later.)
FIG. 3 shows a fixed data table that stores the address parts of the sequence table in FIG. 1.
FIG. 6 shows a detailed data table. Specifically, the data parts of the sequence table in FIG. 1 are stored in this table using the following codes. For example, of the data for step ST3:
output data is coded as 10H;
output mask data as 0FH (because the first 4 data items are blank);
input data as 10H;
input mask data as 0FH (because the first 4 data items are blank);
branch No. 1 as 02H (2 entered);
branch No. 2 as 00H (because this item is blank);
branch No. 3 as 00H (because this item is blank);
monitoring timer value as 10H (provisional); and
step timer value as 10H (provisional).
As another example, of the data for step ST2:
output data is coded as 01H (because the first output alone is set to "1");
output mask data as 00H (because there is no blank);
input data as 06H;
input mask data as 18H;
branch No. 1 as 04 H;
branch No. 2 as 00H;
branch No. 3 as 03H;
monitoring timer value as 64H (100 seconds); and step timer value as 10H.
FIG. 7 shows a variable data table that stores variable information for the sequence table. Illustratively, the step number indicates the current step number. If the sequence is in step ST1, then the number is 01H.
The status flags store the status of the table. FIG. 8 shows the construction of the flags in detail. The run flag controls the execution and stopping of the table. In this example, the flag stays at "1", indicating the execution status.
The input condition check flag is set to a logical "1" if the input value matches its counterpart in the address table, and to a logical "0" if there is a mismatch. For example, when the sequence is in step ST2 of FIG. 1, a logical "1" is set provided that I10=0, I20=1 and I30=1; otherwise a logical "0" is set. Inputs I8 and I9 are blank and thus are not included in the check conditions.
The step timer-up flag is reset by the output process performed at the beginning of a step. When reset, the flag causes the step timer to start with the step timer value of the current step in FIG. 8. When time is up on the step timer, a logical "1" is set.
The monitoring timer-up flag acts in the same manner as the step timer-up flag.
The step transition flag is used to determine if an output process is to be carried out.
The flowchart in FIG. 4 will now be described. When the table execution instruction "EXE-TBL-1" is started, a check is made in step ST10 to see if the run bit, one of the status bits in FIG. 8, is set to "1". If "1" is found to have been set, the next step is reached. In step ST11, a check is made to see if the step transition flag is set to "1". If the flag is "1", then an output process is carried out in step ST12.
The output process mentioned above involves sending designated data to certain addresses for the output address table in the fixed data table. (In step ST2, a "1" is output to 04, a "0" to 05, a "0" to 06 and a "0" to 07. No operation is performed in a blank such as step ST3.) At the same time, the input condition check bit, step timer-up bit and monitoring timer-up bit shown in FIG. 8 are reset. The step timer and the monitoring timer are started accordingly.
Then the step transition flag in FIG. 8 is reset, and the output process is terminated in step ST13. If the step transition flag is not set to "1" in step ST11, an input condition check (FIG. 8) is made in step ST14. The process of the input condition check involves consecutively reading the data of I10, I20, I30, I8 and I9 and checking to see if the data match designated values. If all data match the corresponding designated values, the input condition check bit is set to "1"; otherwise the bit is set to "0". For example, in step ST2, a logical "1" is set if I10="0" I20="1" and I30="1"; otherwise a logical "0" is set. (Since I8 and I9 are blanks, these two conditions are regarded as fulfilled.) Then in step ST15, a timer process is carried out.
The timer process involves updating the up-times for the step timer and monitoring timer which were started in the output process; when a predetermined up-time is reached, the timer-up bit of the step timer or monitoring timer is set. The timer values are designated in each step, as illustrated in FIG. 6. Then in step ST16, a check is made to see if a branch condition is met.
A branch condition being met means that, in step ST2 for example, either the normal M11 (i.e., input condition check bit) is set to "1", or the abnormal M17 (i.e., monitoring timer-up bit) is set to "1". If both conditions are met simultaneously, the one in the upstream of the flow of control, i.e., the normal M11 in this case, takes precedence. Because the timer M12 is left blank, no branch condition is considered met even if M12 is set to "1".
If the result of the branch condition check is positive (YES), a step updating process is carried out in step ST17. This process involves updating a step number shown in FIG. 7. For example, in step ST2, the step number ST2 is replaced by ST4 if the normal M11 branch condition is met. That is, the updating causes ST4 to be the new step number. Then the step transition flag is set in step ST18. This completes all the processes involved.
There will now be explained how to deal with an abnormal state. Here, step ST2 is assumed to be in effect. If no input condition remains fulfilled because the valves 4, 5 and 6 as well as the level switches 10, 20 and 30 are faulty, the monitoring timer-up bit of the abnormal M17 for branch condition No. 3 is set, and step ST3 is reached. In step ST3, the output 015 is set to "1" and the warning lamp goes on. In response, the operator in charge checks the status of the plant and takes appropriate action. If transition is deemed possible, the operator presses the push-button switch 9 to reset the emergency stop. The normal M11 is then set to "1", and step ST2 is reached again. The warning lamp is turned off. If no other problem exists, the normal status is restored.
Likewise in steps ST4 and ST7, when time is up on the monitoring timer, the branch condition of M17 (abnormal) is met. The corresponding status flag is set to "1". Thus the same operations as above are repeated. As indicated, steps ST3, ST5 and ST8 are expended to deal with the abnormal state.
The foregoing description has shown how prior art sequence controllers are generally configured and how they work. It is evident from the description that the address parts of their sequence table are incapable of directly accommodating logical or arithmetic expressions therein. In addition, it has been necessary for the prior art sequence controllers to have additional steps to deal with abnormal states besides those provided in the sequence table. In the sequence table of FIG. 1, three steps, ST3, ST5 and ST8, are provided to address abnormal states. In actual plants, however, a large number of steps in the sequence table must be supplemented by the correspondingly large number of steps to deal with abnormal contingencies. This has resulted in the need to provide a large memory capacity.